To download the design requirements, click here. Look below for design hints, given by Mr. Noman in his lecture (plus for some extra strategies).
Design Strategy & Hints
1. The design can be completed in a total of four stages, with the first three being CE stages (partially of fully bypassed) and a CC stage at the end. The CE stages may be connected in a complementary way (NPN, PNP, NPN), with the last CC stage being NPN.
2. The first stage should preferably be a common emitter without emitter bypass for "good" input impedance i.e. to achieve the required 10 k value. Use the formula of R(in) for CE to make it around 10k.
3. The two middle CE stages can fulfill the desired gain requirements of the design, being partially bypassed. Also, you have to assume a suitable gain for each CE stage.
4. The last stage should be a common collector stage, with zero DC level. It means that if you start designing from the last (CC) stage, its base voltage should be around 0.7 V, which implies that the collector voltage of the second last stage must be 0.7 V.
5. Keep your assumed value of collector current less than 15 mA.
6. You can start designing from either the first stage or the last stage.
7. Keep the CB junction of each transistor reverse biased.
8. Keep the DC output level of each stage nearly 0V, so that the signal does not get clipped at any stage.