That all folks! At last, this ruthless semester is about to come to an end... But before this happens, all of us have to go through a torturous process of, what's commonly known as, "the exams".
Here's the expected date-sheet of the final term exams, starting from 11th of January. Starting time is 1:00 pm and the time given to solve the stuff will be 90 minutes.
(The semester has also been extended for an extra week - Sources)
Here is a bunch of questions, thrown by Mr. Ali Mohsin at some of our fellows living in other sections, in a very ridiculous way indeed:
1. Why do we not use collector resistance in common collector configuration? What are its advantages and disadvantages, if any?
Advantage is transistor's protection in case of some-short circuit and disadvantage is increased output impedance (when not bypassed).
2. What's the advantage of using a dual supply?
To download the design requirements, click here. Look below for design hints, given by Mr. Noman in his lecture (plus for some extra strategies).
Design Strategy & Hints
1. The design can be completed in a total of four stages, with the first three being CE stages (partially of fully bypassed) and a CC stage at the end. The CE stages may be connected in a complementary way (NPN, PNP, NPN), with the last CC stage being NPN.
This link will provide you with a full-fledge sample of upcoming "to be submitted" thermodynamics assignment. Remember to make some "serious" changes in the given stuff, but feel free to copy your required material from the document.
(Only selected users are allowed to download this file!)
Click here to get the extracted samples of design assignments from ANE Lab.
(Only selected users are allowed to download this stuff!)
Click Here (No need to mention "to download......bla bla bla....")